Comprehensive report for FPGA partner covering:
- System architecture and channel model
- LDPC decoder hardware blocks
- Code optimization journey (5.23 -> 1.03 photons/slot)
- SC-LDPC threshold saturation results
- RTL implementation plan and area estimates
Includes 10 figures: system architecture, channel model,
degree distributions, FER curves, threshold progressions.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Run FER validation at Z=128 with normalized min-sum (alpha=0.875).
Best alpha found via sweep: 0.875 (threshold 2.90 photons/slot).
Z=128 matrix achieves girth=8 vs girth=6 at Z=32.
Add Z=128 vs Z=32 FER comparison plot.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Fixed improved staircase: below-diagonal connections preserve full
parity rank (col7->row0 s3, col1->row4 s15)
- Fixed PEG matrix: staircase backbone with cross-connections,
all parity cols dv>=2, VN degrees [7,3,3,3,2,2,2,2]
- Clean up VN degree display (remove np.int64 wrapper)
- Ran all four analyses with 200 frames per point
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
