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cah 77103f68c6 fix(decoder): replace serial popcount with balanced adder tree for timing closure

Split SYNDROME state into SYNDROME_S1 (parity computation) + SYNDROME_S2
(popcount) pipeline stages. SYNDROME_S2 uses a 4-level balanced adder tree
(224→56→14→4→1) instead of a serial accumulator loop, eliminating the
loop-carried dependency that Yosys could not optimize. This reduces the
critical path from ~48 ns to ~14 ns, achieving WNS=0.0 at TT corner (50 MHz).

Verilator verified: 2/2 basic + 20/20 vector tests pass.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-03-05 05:18:57 -07:00

data

feat: add test vector generation for RTL verification

2026-02-25 18:36:26 -07:00

docs

docs: add OpenLane hardening results and critical path analysis

2026-03-02 17:03:35 -07:00

model

test: add vector-driven Verilator testbench with Python model cross-check

2026-02-25 19:50:09 -07:00

rtl

fix(decoder): replace serial popcount with balanced adder tree for timing closure