cah
ab9ef9ca30
Add gen_verilator_vectors.py to convert test_vectors.json into hex files for $readmemh, and tb_ldpc_vectors.sv to drive 20 test vectors through the RTL decoder and verify bit-exact matching against the Python model. All 11 converged vectors pass with exact decoded word, convergence flag, and zero syndrome weight. All 9 non-converged vectors match the Python model's decoded word, iteration count, and syndrome weight exactly. Three RTL bugs fixed in ldpc_decoder_core.sv during testing: - Magnitude overflow: -32 (6'b100000) negation overflowed 5-bit field to 0; now clamped to max magnitude 31 - Converged flag persistence: moved clearing from IDLE to INIT so host can read results after decode completes - msg_cn2vn zeroing: bypass stale array reads on first iteration (iter_cnt==0) to avoid Verilator scheduling issues with large 3D array initialization Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
445 lines
18 KiB
Systemverilog
445 lines
18 KiB
Systemverilog
// LDPC Decoder Core - Layered Min-Sum with QC structure
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//
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// Layered scheduling processes one base-matrix row at a time.
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// For each row, we:
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// 1. Read VN beliefs for all Z columns connected to this row
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// 2. Subtract old CN->VN messages to get VN->CN messages
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// 3. Run CN min-sum update
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// 4. Add new CN->VN messages back to VN beliefs
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// 5. Write updated beliefs back
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//
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// This converges ~2x faster than flooding and needs only one message memory
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// (CN->VN messages for current layer, overwritten each layer).
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module ldpc_decoder_core #(
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parameter N_BASE = 8,
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parameter M_BASE = 7,
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parameter Z = 32,
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parameter N = N_BASE * Z,
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parameter M = M_BASE * Z,
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parameter Q = 6,
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parameter MAX_ITER = 30,
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parameter DC = 8, // check node degree
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parameter DV_MAX = 7 // max variable node degree
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)(
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input logic clk,
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input logic rst_n,
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// Control
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input logic start,
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input logic early_term_en,
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input logic [4:0] max_iter,
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// Channel LLRs (loaded before start)
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input logic signed [Q-1:0] llr_in [N],
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// Status
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output logic busy,
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output logic converged,
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output logic [4:0] iter_used,
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// Results
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output logic [Z-1:0] decoded_bits, // first Z bits = info bits
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output logic [7:0] syndrome_weight
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);
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// =========================================================================
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// Base matrix H stored as shift values (-1 = no connection)
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// H_BASE[row][col] = cyclic shift amount, or -1 if zero sub-matrix
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// =========================================================================
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// IRA staircase base matrix for rate-1/8 QC-LDPC
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// Column 0 = info (dv=7), Columns 1-7 = parity with lower-triangular staircase
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// This matches model/ldpc_sim.py exactly.
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//
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// Row 0: info(0) + p1(5)
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// Row 1: info(11) + p1(3) + p2(0)
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// Row 2: info(17) + p2(7) + p3(0)
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// Row 3: info(23) + p3(13) + p4(0)
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// Row 4: info(29) + p4(19) + p5(0)
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// Row 5: info(3) + p5(25) + p6(0)
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// Row 6: info(9) + p6(31) + p7(0)
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logic signed [5:0] H_BASE [M_BASE][N_BASE];
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initial begin
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// Row 0: cols 0,1 connected
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H_BASE[0][0] = 0; H_BASE[0][1] = 5; H_BASE[0][2] = -1;
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H_BASE[0][3] = -1; H_BASE[0][4] = -1; H_BASE[0][5] = -1;
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H_BASE[0][6] = -1; H_BASE[0][7] = -1;
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// Row 1: cols 0,1,2 connected
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H_BASE[1][0] = 11; H_BASE[1][1] = 3; H_BASE[1][2] = 0;
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H_BASE[1][3] = -1; H_BASE[1][4] = -1; H_BASE[1][5] = -1;
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H_BASE[1][6] = -1; H_BASE[1][7] = -1;
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// Row 2: cols 0,2,3 connected
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H_BASE[2][0] = 17; H_BASE[2][1] = -1; H_BASE[2][2] = 7;
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H_BASE[2][3] = 0; H_BASE[2][4] = -1; H_BASE[2][5] = -1;
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H_BASE[2][6] = -1; H_BASE[2][7] = -1;
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// Row 3: cols 0,3,4 connected
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H_BASE[3][0] = 23; H_BASE[3][1] = -1; H_BASE[3][2] = -1;
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H_BASE[3][3] = 13; H_BASE[3][4] = 0; H_BASE[3][5] = -1;
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H_BASE[3][6] = -1; H_BASE[3][7] = -1;
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// Row 4: cols 0,4,5 connected
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H_BASE[4][0] = 29; H_BASE[4][1] = -1; H_BASE[4][2] = -1;
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H_BASE[4][3] = -1; H_BASE[4][4] = 19; H_BASE[4][5] = 0;
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H_BASE[4][6] = -1; H_BASE[4][7] = -1;
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// Row 5: cols 0,5,6 connected
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H_BASE[5][0] = 3; H_BASE[5][1] = -1; H_BASE[5][2] = -1;
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H_BASE[5][3] = -1; H_BASE[5][4] = -1; H_BASE[5][5] = 25;
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H_BASE[5][6] = 0; H_BASE[5][7] = -1;
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// Row 6: cols 0,6,7 connected
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H_BASE[6][0] = 9; H_BASE[6][1] = -1; H_BASE[6][2] = -1;
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H_BASE[6][3] = -1; H_BASE[6][4] = -1; H_BASE[6][5] = -1;
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H_BASE[6][6] = 31; H_BASE[6][7] = 0;
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end
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// =========================================================================
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// Memory: VN beliefs (total posterior LLR per bit)
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// beliefs[j] = channel_llr[j] + sum of all CN->VN messages to j
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// =========================================================================
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logic signed [Q-1:0] beliefs [N];
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// =========================================================================
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// Memory: CN->VN messages for layered update
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// msg_cn2vn[row][col][z] = message from check (row*Z+z) to variable (col*Z+shift(z))
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// Stored as [M_BASE][N_BASE] banks of Z entries each
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// =========================================================================
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logic signed [Q-1:0] msg_cn2vn [M_BASE][N_BASE][Z];
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// =========================================================================
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// Decoder FSM
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// =========================================================================
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typedef enum logic [3:0] {
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IDLE,
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INIT, // Initialize beliefs from channel LLRs, zero messages
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LAYER_READ, // Read Z beliefs for each of DC columns in current row
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CN_UPDATE, // Run min-sum CN update on gathered messages
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LAYER_WRITE, // Write updated beliefs and new CN->VN messages
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SYNDROME, // Check syndrome after full iteration
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SYNDROME_DONE, // Read registered syndrome result
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DONE
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} state_t;
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state_t state, state_next;
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logic [4:0] iter_cnt;
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logic [2:0] row_idx; // current base matrix row (0..M_BASE-1)
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logic [2:0] col_idx; // current column being read/written (0..N_BASE-1)
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logic [4:0] effective_max_iter;
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// Working registers for current layer CN update
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logic signed [Q-1:0] vn_to_cn [DC][Z]; // VN->CN messages for current row
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logic signed [Q-1:0] cn_to_vn [DC][Z]; // new CN->VN messages (output of min-sum)
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// Syndrome check
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logic [7:0] syndrome_cnt;
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logic syndrome_ok;
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assign effective_max_iter = (max_iter == 0) ? MAX_ITER[4:0] : max_iter;
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assign busy = (state != IDLE) && (state != DONE);
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// =========================================================================
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// State machine
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// =========================================================================
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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end else begin
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state <= state_next;
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end
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end
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always_comb begin
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state_next = state;
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case (state)
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IDLE: if (start) state_next = INIT;
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INIT: state_next = LAYER_READ;
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LAYER_READ: if (col_idx == N_BASE - 1) state_next = CN_UPDATE;
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CN_UPDATE: state_next = LAYER_WRITE;
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LAYER_WRITE: begin
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if (col_idx == N_BASE - 1) begin
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if (row_idx == M_BASE - 1)
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state_next = SYNDROME;
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else
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state_next = LAYER_READ; // next row
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end
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end
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SYNDROME: state_next = SYNDROME_DONE;
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SYNDROME_DONE: begin
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if (syndrome_ok && early_term_en)
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state_next = DONE;
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else if (iter_cnt >= effective_max_iter)
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state_next = DONE;
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else
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state_next = LAYER_READ; // next iteration
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end
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DONE: if (!start) state_next = IDLE;
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default: state_next = IDLE;
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endcase
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end
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// =========================================================================
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// Datapath
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// =========================================================================
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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iter_cnt <= '0;
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row_idx <= '0;
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col_idx <= '0;
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converged <= 1'b0;
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iter_used <= '0;
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syndrome_weight <= '0;
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syndrome_ok <= 1'b0;
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end else begin
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case (state)
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IDLE: begin
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iter_cnt <= '0;
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row_idx <= '0;
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col_idx <= '0;
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// Note: converged, iter_used, syndrome_weight, decoded_bits
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// are NOT cleared here so the host can read them after decode.
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// They are cleared in INIT when a new decode starts.
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end
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INIT: begin
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// Initialize beliefs from channel LLRs
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for (int j = 0; j < N; j++) begin
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beliefs[j] <= llr_in[j];
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end
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// Zero all CN->VN messages
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for (int r = 0; r < M_BASE; r++)
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for (int c = 0; c < N_BASE; c++)
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for (int z = 0; z < Z; z++)
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msg_cn2vn[r][c][z] <= {Q{1'b0}};
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row_idx <= '0;
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col_idx <= '0;
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iter_cnt <= '0;
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converged <= 1'b0;
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syndrome_ok <= 1'b0;
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end
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LAYER_READ: begin
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// For column col_idx in current row_idx:
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// VN->CN = belief - old CN->VN message
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// (belief already contains the sum of ALL CN->VN messages,
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// so subtracting the current row's message gives the extrinsic)
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// Skip unconnected columns (H_BASE == -1)
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if (H_BASE[row_idx][col_idx] >= 0) begin
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for (int z = 0; z < Z; z++) begin
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int bit_idx;
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int shifted_z;
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logic signed [Q-1:0] old_msg;
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logic signed [Q-1:0] belief_val;
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shifted_z = (z + H_BASE[row_idx][col_idx]) % Z;
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bit_idx = int'(col_idx) * Z + shifted_z;
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// On first iteration (iter_cnt==0), old messages are zero
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// since no CN update has run yet. Use 0 directly rather
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// than reading msg_cn2vn, which may not be reliably zeroed
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// by the INIT state in all simulation tools.
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old_msg = (iter_cnt == 0) ?
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{Q{1'b0}} : msg_cn2vn[row_idx][col_idx][z];
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belief_val = beliefs[bit_idx];
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vn_to_cn[col_idx][z] <= sat_sub(belief_val, old_msg);
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end
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end else begin
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// Unconnected: set to +MAX so magnitude doesn't affect min-sum
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for (int z = 0; z < Z; z++)
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vn_to_cn[col_idx][z] <= {1'b0, {(Q-1){1'b1}}}; // +31
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end
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if (col_idx == N_BASE - 1)
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col_idx <= '0;
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else
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col_idx <= col_idx + 1;
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end
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CN_UPDATE: begin
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// Min-sum update for all Z check nodes in current row
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// Each CN has DC=8 incoming messages (one per column)
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for (int z = 0; z < Z; z++) begin
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// Gather DC messages for check node z
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logic signed [Q-1:0] msgs [DC];
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for (int d = 0; d < DC; d++)
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msgs[d] = vn_to_cn[d][z];
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// Min-sum: find min1, min2, sign product, min1 index
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cn_min_sum(msgs, cn_to_vn[0][z], cn_to_vn[1][z],
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cn_to_vn[2][z], cn_to_vn[3][z],
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cn_to_vn[4][z], cn_to_vn[5][z],
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cn_to_vn[6][z], cn_to_vn[7][z]);
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end
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col_idx <= '0; // prepare for LAYER_WRITE
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end
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LAYER_WRITE: begin
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// Write back: update beliefs and store new CN->VN messages
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// Skip unconnected columns (H_BASE == -1)
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if (H_BASE[row_idx][col_idx] >= 0) begin
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for (int z = 0; z < Z; z++) begin
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int bit_idx;
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int shifted_z;
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logic signed [Q-1:0] new_msg;
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logic signed [Q-1:0] old_extrinsic;
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shifted_z = (z + H_BASE[row_idx][col_idx]) % Z;
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bit_idx = int'(col_idx) * Z + shifted_z;
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new_msg = cn_to_vn[col_idx][z];
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old_extrinsic = vn_to_cn[col_idx][z];
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// belief = extrinsic (VN->CN) + new CN->VN message
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beliefs[bit_idx] <= sat_add(old_extrinsic, new_msg);
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// Store new message for next iteration
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msg_cn2vn[row_idx][col_idx][z] <= new_msg;
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end
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end
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if (col_idx == N_BASE - 1) begin
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col_idx <= '0;
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if (row_idx == M_BASE - 1)
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row_idx <= '0;
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else
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row_idx <= row_idx + 1;
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end else begin
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col_idx <= col_idx + 1;
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end
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end
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SYNDROME: begin
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// Check H * c_hat == 0 (compute syndrome weight)
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// Only include connected columns (H_BASE >= 0)
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syndrome_cnt = '0;
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for (int r = 0; r < M_BASE; r++) begin
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for (int z = 0; z < Z; z++) begin
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logic parity;
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parity = 1'b0;
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for (int c = 0; c < N_BASE; c++) begin
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if (H_BASE[r][c] >= 0) begin
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int shifted_z, bit_idx;
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shifted_z = (z + H_BASE[r][c]) % Z;
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bit_idx = c * Z + shifted_z;
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parity = parity ^ beliefs[bit_idx][Q-1];
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end
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end
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if (parity) syndrome_cnt = syndrome_cnt + 1;
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end
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end
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syndrome_weight <= syndrome_cnt;
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syndrome_ok <= (syndrome_cnt == 0);
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iter_cnt <= iter_cnt + 1;
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iter_used <= iter_cnt + 1;
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end
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SYNDROME_DONE: begin
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// Check registered syndrome result
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if (syndrome_ok) converged <= 1'b1;
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end
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DONE: begin
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// Output decoded info bits (first Z=32 bits, column 0)
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for (int z = 0; z < Z; z++)
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decoded_bits[z] <= beliefs[z][Q-1]; // sign bit = hard decision
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end
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endcase
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end
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end
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// =========================================================================
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// Min-sum CN update function
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// =========================================================================
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// Offset min-sum for DC=8 inputs
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// For each output j: sign = XOR of all other signs, magnitude = min of all other magnitudes - offset
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task automatic cn_min_sum(
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input logic signed [Q-1:0] in [DC],
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output logic signed [Q-1:0] out0, out1, out2, out3,
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out4, out5, out6, out7
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);
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logic [DC-1:0] signs;
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logic [Q-2:0] mags [DC];
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logic sign_xor;
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logic [Q-2:0] min1, min2;
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int min1_idx;
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logic signed [Q-1:0] outs [DC];
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// Extract signs and magnitudes
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// Note: -32 (100000) has magnitude 32 which overflows 5-bit field to 0.
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// Clamp to 31 (max representable magnitude) to avoid corruption.
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sign_xor = 1'b0;
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for (int i = 0; i < DC; i++) begin
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logic [Q-1:0] abs_val; // wider to detect overflow
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signs[i] = in[i][Q-1];
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if (in[i][Q-1]) begin
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abs_val = ~in[i] + 1'b1;
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// If abs_val overflowed (input was most negative), clamp
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mags[i] = (abs_val[Q-1]) ? {(Q-1){1'b1}} : abs_val[Q-2:0];
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end else begin
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mags[i] = in[i][Q-2:0];
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end
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sign_xor = sign_xor ^ signs[i];
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end
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// Find two smallest magnitudes
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min1 = {(Q-1){1'b1}};
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min2 = {(Q-1){1'b1}};
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min1_idx = 0;
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for (int i = 0; i < DC; i++) begin
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if (mags[i] < min1) begin
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min2 = min1;
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min1 = mags[i];
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min1_idx = i;
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end else if (mags[i] < min2) begin
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min2 = mags[i];
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end
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end
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// Compute extrinsic outputs with offset correction
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for (int j = 0; j < DC; j++) begin
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logic [Q-2:0] mag_out;
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logic sign_out;
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mag_out = (j == min1_idx) ? min2 : min1;
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// Offset correction (subtract 1 in integer representation)
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mag_out = (mag_out > 1) ? (mag_out - 1) : {(Q-1){1'b0}};
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sign_out = sign_xor ^ signs[j];
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outs[j] = sign_out ? (~{1'b0, mag_out} + 1) : {1'b0, mag_out};
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end
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out0 = outs[0]; out1 = outs[1]; out2 = outs[2]; out3 = outs[3];
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out4 = outs[4]; out5 = outs[5]; out6 = outs[6]; out7 = outs[7];
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endtask
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// =========================================================================
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// Saturating arithmetic helpers
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// =========================================================================
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function automatic logic signed [Q-1:0] sat_add(
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logic signed [Q-1:0] a, logic signed [Q-1:0] b
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);
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logic signed [Q:0] sum;
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sum = {a[Q-1], a} + {b[Q-1], b}; // sign-extend and add
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if (sum > $signed({1'b0, {(Q-1){1'b1}}}))
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return {1'b0, {(Q-1){1'b1}}}; // +max
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else if (sum < $signed({1'b1, {(Q-1){1'b0}}}))
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return {1'b1, {(Q-1){1'b0}}}; // -max
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else
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return sum[Q-1:0];
|
|
endfunction
|
|
|
|
function automatic logic signed [Q-1:0] sat_sub(
|
|
logic signed [Q-1:0] a, logic signed [Q-1:0] b
|
|
);
|
|
return sat_add(a, -b);
|
|
endfunction
|
|
|
|
endmodule
|