Add gen_verilator_vectors.py to convert test_vectors.json into hex files
for $readmemh, and tb_ldpc_vectors.sv to drive 20 test vectors through
the RTL decoder and verify bit-exact matching against the Python model.
All 11 converged vectors pass with exact decoded word, convergence flag,
and zero syndrome weight. All 9 non-converged vectors match the Python
model's decoded word, iteration count, and syndrome weight exactly.
Three RTL bugs fixed in ldpc_decoder_core.sv during testing:
- Magnitude overflow: -32 (6'b100000) negation overflowed 5-bit field
to 0; now clamped to max magnitude 31
- Converged flag persistence: moved clearing from IDLE to INIT so host
can read results after decode completes
- msg_cn2vn zeroing: bypass stale array reads on first iteration
(iter_cnt==0) to avoid Verilator scheduling issues with large 3D
array initialization
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add tb/tb_ldpc_decoder.sv with Wishbone read/write tasks, version
register test, and all-zero codeword decode test. Add tb/Makefile
with lint and sim targets.
Fix two RTL bugs found during testbench bring-up:
- ldpc_decoder_core.sv: skip unconnected H_BASE columns (shift=-1)
in LAYER_READ, LAYER_WRITE, and SYNDROME states to prevent
out-of-bounds array access and belief corruption
- ldpc_decoder_core.sv: fix syndrome_ok timing race by adding
SYNDROME_DONE state so the registered result is available before
the early-termination decision
- wishbone_interface.sv: fix VERSION_ID typo (0xLD01 -> 0x1D01)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
IRA staircase structure: col 0 = info (dv=7), cols 1-7 = parity (dv=1-2).
RTL decoder core still needs CN update rework for variable degree.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
