cah b8bff512a4 Add implementation plan for frame sync and code analysis ...

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-02-24 04:58:56 -07:00

data

Fix matrix rank issues and run all code analyses

2026-02-24 04:56:37 -07:00

docs/plans

Add implementation plan for frame sync and code analysis

2026-02-24 04:58:56 -07:00

model

Fix matrix rank issues and run all code analyses

2026-02-24 04:56:37 -07:00

rtl

Update RTL base matrix to match working Python model

2026-02-23 21:56:48 -07:00

CLAUDE.md

Initial LDPC optical decoder project scaffold

2026-02-23 21:47:40 -07:00

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SystemVerilog 17.6%

Makefile 0.4%