cah f2901c6366 docs: add OpenLane hardening results and critical path analysis ...

Documents 4 hardening runs with timing/area/DRC results. Identifies
SYNDROME state as critical path bottleneck (222 logic levels, 49 ns)
and proposes 2-stage pipeline fix to meet 50 MHz target.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-03-02 17:03:35 -07:00

..

plans

docs: add detailed implementation plan for ChipFoundry contest

2026-02-25 18:10:38 -07:00

analysis-results.md

Add comprehensive analysis results document

2026-02-24 05:01:26 -07:00

hardening-results.md

docs: add OpenLane hardening results and critical path analysis

2026-03-02 17:03:35 -07:00

project_report.md

docs: frame sync runs as PicoRV32 firmware, zero extra RTL

2026-02-24 22:47:49 -07:00