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cah f2901c6366 docs: add OpenLane hardening results and critical path analysis

Documents 4 hardening runs with timing/area/DRC results. Identifies
SYNDROME state as critical path bottleneck (222 logic levels, 49 ns)
and proposes 2-stage pipeline fix to meet 50 MHz target.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-03-02 17:03:35 -07:00

data

feat: add test vector generation for RTL verification

2026-02-25 18:36:26 -07:00

docs

docs: add OpenLane hardening results and critical path analysis

2026-03-02 17:03:35 -07:00

model

test: add vector-driven Verilator testbench with Python model cross-check

2026-02-25 19:50:09 -07:00

rtl

fix: sync Yosys-compatible sat_add/sat_sub from chip_ignite