3 Commits

Author	SHA1	Message	Date
cah	87b84f8c75	docs: add project report with architecture diagrams ... Comprehensive report for FPGA partner covering: - System architecture and channel model - LDPC decoder hardware blocks - Code optimization journey (5.23 -> 1.03 photons/slot) - SC-LDPC threshold saturation results - RTL implementation plan and area estimates Includes 10 figures: system architecture, channel model, degree distributions, FER curves, threshold progressions. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>	2026-02-24 21:45:35 -07:00
cah	b4d5856bf9	data: add SC-LDPC results and comprehensive comparison plots ... SC-LDPC threshold saturation results: - SC original staircase: 2.28 photons/slot (vs 4.76 uncoupled) - SC DE-optimized: 1.03 photons/slot (vs 3.21 uncoupled) - Shannon limit: 0.47 photons/slot (remaining gap: 3.4 dB) Add CLI to sc_ldpc.py (threshold, fer-compare, full subcommands). Add threshold progression, SC threshold bars, and SC FER plots. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>	2026-02-24 18:35:50 -07:00
cah	49c494401b	data: add Z=128 pipeline results and comparison plots ... Run FER validation at Z=128 with normalized min-sum (alpha=0.875). Best alpha found via sweep: 0.875 (threshold 2.90 photons/slot). Z=128 matrix achieves girth=8 vs girth=6 at Z=32. Add Z=128 vs Z=32 FER comparison plot. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>	2026-02-24 17:08:07 -07:00