Documents 4 hardening runs with timing/area/DRC results. Identifies
SYNDROME state as critical path bottleneck (222 logic levels, 49 ns)
and proposes 2-stage pipeline fix to meet 50 MHz target.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add gen_verilator_vectors.py to convert test_vectors.json into hex files
for $readmemh, and tb_ldpc_vectors.sv to drive 20 test vectors through
the RTL decoder and verify bit-exact matching against the Python model.
All 11 converged vectors pass with exact decoded word, convergence flag,
and zero syndrome weight. All 9 non-converged vectors match the Python
model's decoded word, iteration count, and syndrome weight exactly.
Three RTL bugs fixed in ldpc_decoder_core.sv during testing:
- Magnitude overflow: -32 (6'b100000) negation overflowed 5-bit field
to 0; now clamped to max magnitude 31
- Converged flag persistence: moved clearing from IDLE to INIT so host
can read results after decode completes
- msg_cn2vn zeroing: bypass stale array reads on first iteration
(iter_cnt==0) to avoid Verilator scheduling issues with large 3D
array initialization
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add tb/tb_ldpc_decoder.sv with Wishbone read/write tasks, version
register test, and all-zero codeword decode test. Add tb/Makefile
with lint and sim targets.
Fix two RTL bugs found during testbench bring-up:
- ldpc_decoder_core.sv: skip unconnected H_BASE columns (shift=-1)
in LAYER_READ, LAYER_WRITE, and SYNDROME states to prevent
out-of-bounds array access and belief corruption
- ldpc_decoder_core.sv: fix syndrome_ok timing race by adding
SYNDROME_DONE state so the registered result is available before
the early-termination decision
- wishbone_interface.sv: fix VERSION_ID typo (0xLD01 -> 0x1D01)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Improve generate_test_vectors() to use mixed SNR levels (high SNR for
first half, nominal for second half) ensuring a mix of converged and
non-converged test cases. Add gen_firmware_vectors.py converter that
reads test_vectors.json and produces packed LLR data matching the
RTL wishbone interface format (5 LLRs per 32-bit word, 6-bit two's
complement).
Generated 20 vectors: 11 converged, 9 non-converged.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
20 tasks across 8 weeks covering RTL integration, verification,
OpenLane hardening, firmware, PCBA, and final submission.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Approach A (minimal viable submission) as execution plan,
Approaches B and C documented as aspirational roadmap.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Reuses existing syndrome_wt register and converged flag.
No additional hardware needed on the ASIC.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Adds section 7 covering preamble-less frame sync using syndrome
screening, which was missing from the original report.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Comprehensive report for FPGA partner covering:
- System architecture and channel model
- LDPC decoder hardware blocks
- Code optimization journey (5.23 -> 1.03 photons/slot)
- SC-LDPC threshold saturation results
- RTL implementation plan and area estimates
Includes 10 figures: system architecture, channel model,
degree distributions, FER curves, threshold progressions.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Implement position-aware density evolution for SC-LDPC codes:
- sc_density_evolution(): flooding-schedule DE tracking per-position
error rates, demonstrating the wave decoding effect
- compute_sc_threshold(): binary search for SC-LDPC threshold
Uses flooding schedule (not layered) to avoid belief divergence
from cross-position message interference in the coupled chain.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Run FER validation at Z=128 with normalized min-sum (alpha=0.875).
Best alpha found via sweep: 0.875 (threshold 2.90 photons/slot).
Z=128 matrix achieves girth=8 vs girth=6 at Z=32.
Add Z=128 vs Z=32 FER comparison plot.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Implement windowed_decode() for SC-LDPC codes using flooding
min-sum with sliding window of W positions. Supports both
normalized and offset min-sum modes.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Implement spatially-coupled LDPC code construction with:
- split_protograph(): split base matrix edges into w components
- build_sc_chain(): build full SC-LDPC H matrix with L positions
- sc_encode(): GF(2) Gaussian elimination encoder for SC chain
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Make validate_matrix() and run_full_pipeline() accept z parameter
instead of using hardcoded Z=32. Thread cn_mode/alpha to validation.
Add --z/--cn-mode/--alpha CLI options to full pipeline.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add optimize_alpha() function that sweeps hardware-friendly alpha
values to find the best DE threshold with normalized min-sum.
Add alpha-sweep CLI subcommand and --z/--cn-mode/--alpha options
to the full pipeline.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Thread cn_mode and alpha parameters through the entire DE pipeline:
de_cn_update_vectorized(), density_evolution_step(), run_de(),
compute_threshold(), and compute_threshold_for_profile().
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add cn_mode ('offset'/'normalized') and alpha parameters to
min_sum_cn_update() in ldpc_sim.py and generic_decode() in
ldpc_analysis.py. Normalized mode scales magnitudes by alpha
(default 0.75) instead of subtracting a fixed offset, which
is better suited for low-rate codes.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Covers all five studies: rate comparison, base matrix quality,
quantization sweep, Shannon gap, and frame synchronization.
Includes interpretation, recommendations, and reproduction steps.
Key findings: 9 dB gap to Shannon, matrix degree distribution is
the primary bottleneck, 6-bit quantization validated, frame sync
tractable at ~30 us acquisition cost.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Fixed improved staircase: below-diagonal connections preserve full
parity rank (col7->row0 s3, col1->row4 s15)
- Fixed PEG matrix: staircase backbone with cross-connections,
all parity cols dv>=2, VN degrees [7,3,3,3,2,2,2,2]
- Clean up VN degree display (remove np.int64 wrapper)
- Ran all four analyses with 200 frames per point
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Implements four LDPC code analyses for photon-starved optical channels:
- Rate sweep: compare FER across 1/2, 1/3, 1/4, 1/6, 1/8 IRA staircase codes
- Matrix comparison: original staircase vs improved staircase vs PEG ring
- Quantization sweep: 4-16 bit and float precision impact on FER
- Shannon gap: binary-input Poisson channel capacity limits via binary search
Core infrastructure includes generic IRA staircase builder, GF(2) Gaussian
elimination encoder for non-triangular matrices, parameterized layered
min-sum decoder with variable check degree, and BFS girth computation.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Covers frame synchronization prototype (acquisition + re-sync)
and four code analysis studies: rate comparison, base matrix
quality, quantization sweep, and Shannon gap computation.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
IRA staircase structure: col 0 = info (dv=7), cols 1-7 = parity (dv=1-2).
RTL decoder core still needs CN update rework for variable degree.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Fixed cyclic shift convention (QC-LDPC P_s is left shift, not right)
- Fixed encoder to solve rows sequentially (row 0 first for p1, then 1-6)
- Fixed decoder to only gather connected columns per CN (staircase has dc=2-3)
- Fixed LLR sign convention: positive = bit 0 more likely
- Decoder validates at lam_s >= 4 photons/slot (~90% frame success)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
