IRA staircase structure: col 0 = info (dv=7), cols 1-7 = parity (dv=1-2).
RTL decoder core still needs CN update rework for variable degree.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Fixed cyclic shift convention (QC-LDPC P_s is left shift, not right)
- Fixed encoder to solve rows sequentially (row 0 first for p1, then 1-6)
- Fixed decoder to only gather connected columns per CN (staircase has dc=2-3)
- Fixed LLR sign convention: positive = bit 0 more likely
- Decoder validates at lam_s >= 4 photons/slot (~90% frame success)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>