cah 77103f68c6 fix(decoder): replace serial popcount with balanced adder tree for timing closure ...

Split SYNDROME state into SYNDROME_S1 (parity computation) + SYNDROME_S2
(popcount) pipeline stages. SYNDROME_S2 uses a 4-level balanced adder tree
(224→56→14→4→1) instead of a serial accumulator loop, eliminating the
loop-carried dependency that Yosys could not optimize. This reduces the
critical path from ~48 ns to ~14 ns, achieving WNS=0.0 at TT corner (50 MHz).

Verilator verified: 2/2 basic + 20/20 vector tests pass.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-03-05 05:18:57 -07:00

..

ldpc_decoder_core.sv

fix(decoder): replace serial popcount with balanced adder tree for timing closure

2026-03-05 05:18:57 -07:00

ldpc_decoder_top.sv

fix: sync Yosys-compatible packed LLR interface from chip_ignite

2026-02-25 21:08:49 -07:00

wishbone_interface.sv

fix: sync Yosys-compatible packed LLR interface from chip_ignite

2026-02-25 21:08:49 -07:00