cah
db06a8a481
Approach A (minimal viable submission) as execution plan, Approaches B and C documented as aspirational roadmap. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
275 lines
12 KiB
Markdown
275 lines
12 KiB
Markdown
# ChipFoundry Reference Application Design Contest — Submission Design
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**Date:** 2026-02-25
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**Contest:** https://chipfoundry.io/challenges/application/
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**Proposal deadline:** March 25, 2026
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**Final submission deadline:** April 30, 2026
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**Tape-out shuttle:** May 13, 2026
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## Decisions
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| Decision | Choice |
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| Application | Free-space optical communication demo |
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| Clock target | 50–75 MHz (Sky130) |
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| Detector | BAE Systems GMAPD (reference design), cheaper stand-in for demo |
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| Demo strategy | Wishbone loopback — PicoRV32 firmware injects LLRs, no optical link |
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| Companion processor | PicoRV32 (internal to Caravel) — zero external logic |
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| License | Apache 2.0 |
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| Approach | A (Minimal Viable Submission), with B and C documented as aspirational |
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---
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## Approach A: Minimal Viable Submission (EXECUTING)
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Focus on what the judges score: working silicon, verification rigor, and reproducibility.
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### System Architecture
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```
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PicoRV32 (Caravel management SoC)
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| Internal Wishbone B4 bus
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ldpc_decoder_top (user project area, ~1.5 mm²)
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├── wishbone_interface — register map, LLR input, decoded output
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├── ldpc_decoder_core — layered offset min-sum, 7x8 QC-LDPC, Z=32
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└── (hard_decision_out) — packed in core already
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```
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**Data flow:**
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1. PicoRV32 firmware computes channel LLRs (Poisson model) or loads test vectors
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2. Firmware writes 256 quantized 6-bit LLRs to decoder via Wishbone (52 writes, 5 LLRs/word)
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3. Firmware writes CTRL register to start decode (max_iter=30, early_term=1)
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4. Decoder runs layered min-sum iterations, checks syndrome each iteration
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5. Firmware polls STATUS or waits for IRQ
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6. Firmware reads 32 decoded bits + syndrome weight via Wishbone
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7. Firmware reports results over UART
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**Clock:** Single clock domain — `wb_clk_i` from Caravel, target 50–75 MHz.
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**GPIO usage (minimal for loopback demo):**
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- UART TX/RX (2 pins) — already routed through Caravel management SoC
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- Optional: 1–2 status LEDs, decode-busy, decode-done
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- GMAPD connector footprint: reserved pins for future optical frontend
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**No changes to existing RTL module interfaces needed** — the Wishbone interface already matches Caravel's bus signals. Integration is wiring `ldpc_decoder_top` into `user_project_wrapper.v` in place of `user_proj_example`.
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### Verification Strategy
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Three layers of verification, mapped to contest scoring criteria.
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**Layer 1 — cocotb Functional Tests (in chip_ignite/verilog/dv/cocotb/):**
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| Test | What it proves |
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| `ldpc_wb_write_read` | Wishbone register access — write LLRs, read status/version |
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| `ldpc_decode_clean` | Decode a valid codeword (zero-noise) — converges in 1 iteration, syndrome=0 |
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| `ldpc_decode_noisy` | Decode a noisy codeword (known errors) — converges, matches Python reference |
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| `ldpc_decode_max_iter` | Uncorrectable codeword — hits max iterations, syndrome≠0, busy clears |
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| `ldpc_early_term` | Early termination enable/disable — verify iteration count differs |
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| `ldpc_back_to_back` | Two consecutive decodes without reset — no state leakage |
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**Layer 2 — Python Model Cross-Check:**
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- Python model generates test vectors (LLR inputs + expected decoded bits) at multiple SNR points
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- cocotb tests load these vectors and compare RTL output bit-exact against Python reference
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- Covers the Poisson channel model at lambda_s = 0.5, 1.0, 2.0, 5.0 photons/slot
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**Layer 3 — Gate-Level Simulation (GLS):**
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- Re-run Layer 1 tests against post-synthesis netlist (`cf verify <test> --sim gl`)
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- Proves the design survives synthesis + place-and-route
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- Required by contest rules
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**STA (Static Timing Analysis):**
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- SDC constraints targeting 50 MHz (20 ns period) with stretch goal of 75 MHz (13.3 ns)
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- Run `make caravel-sta` after hardening
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- Report WNS/TNS in documentation
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### Firmware
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Bare-metal C running on PicoRV32 inside Caravel.
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**Functions:**
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- `ldpc_load_llrs(int8_t llrs[256])` — packs 5 LLRs per word, writes 52 Wishbone transactions
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- `ldpc_start_decode(uint8_t max_iter, bool early_term)` — writes CTRL register
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- `ldpc_poll_status()` — spins on STATUS register until busy=0
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- `ldpc_read_result(uint32_t *decoded, uint16_t *syndrome_wt, uint8_t *iters)` — reads output registers
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- `uart_print_result()` — formats and prints to UART for demo
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**Demo scenarios (run sequentially on boot):**
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1. **Clean codeword** — encode known 32-bit message, load as perfect LLRs, decode, verify. Prints: `PASS: clean decode, 1 iteration`
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2. **Noisy codeword** — pre-stored test vector with known errors, decode, verify. Prints: `PASS: noisy decode, 8 iterations, syndrome=0`
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3. **Stress test** — loop 100 decodes with different pre-stored vectors, report pass/fail count and average iterations
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No LLR computation from optical data in firmware — that's future work (Approach B/C). All test vectors are compiled into the firmware binary.
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Build: Standard Caravel firmware Makefile (GCC cross-compile for RV32I, link against Caravel BSP).
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### PCBA Reference Design
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Two-part board design in KiCad.
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**Part A — Fabricated for demo (minimal breakout):**
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- Caravel QFN-64 socket with proper decoupling (1.8V core, 3.3V I/O)
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- 25 MHz crystal oscillator (Caravel reference clock)
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- 3.3V and 1.8V LDO regulators (USB-powered or barrel jack)
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- FTDI USB-UART bridge for firmware console
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- SPI flash for firmware storage
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- Reset button, power LED, 2x status LEDs
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- 2-layer board, standard FR4, JLCPCB-friendly
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**Part B — Documented but unpopulated (optical frontend):**
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- GMAPD connector footprint (BAE Systems detector interface)
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- TIA (transimpedance amplifier) section — reference schematic with AD8015 or similar
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- Comparator/discriminator — converts analog pulse to digital timestamp
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- Bias voltage supply for GMAPD (high-voltage section, isolated)
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- SMA connector for external clock sync
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- All components in BOM with Digi-Key part numbers, but DNP for initial build
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**Board size:** ~50x80mm, fits a standard 3D-printed enclosure.
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**Mechanical:** Simple 3D-printed box (OpenSCAD parametric), standoffs for PCB mount, cutouts for USB, barrel jack, and SMA. STL files included in repo.
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### OpenLane Hardening & Tape-out Flow
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**Macro hardening (`ldpc_decoder_top`):**
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- Copy RTL files into `chip_ignite/verilog/rtl/`
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- Create `chip_ignite/openlane/ldpc_decoder_top/config.json`:
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- `CLOCK_PERIOD`: 20 ns (50 MHz), tighten to 13.3 ns (75 MHz) if timing allows
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- `CLOCK_PORT`: `wb_clk_i`
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- `DIE_AREA`: sized for ~1.5 mm² (~1200x1250 um)
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- Sky130 standard cells, no hard macros (all SRAM is register-based)
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- Pin ordering config matching wrapper placement
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- SDC constraints with input/output delays for Wishbone interface
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**Wrapper integration (`user_project_wrapper`):**
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- Replace `user_proj_example` instantiation with `ldpc_decoder_top`
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- Update macro placement coordinates in wrapper `config.json`
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- Point to hardened GDS/LEF/netlist/SPEF
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**Flow sequence:**
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```
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cf harden ldpc_decoder_top # Synthesize + P&R the decoder
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cf harden user_project_wrapper # Integrate into Caravel
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cf gpio-config # Configure GPIO modes
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cf verify --all # RTL + GL sim
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cf precheck # Shuttle compliance
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```
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**Timing closure strategy:**
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- Start at 50 MHz (20 ns) — likely first-pass clean
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- If WNS > 5 ns, tighten to 75 MHz (13.3 ns)
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- If negative WNS at 75 MHz, pipeline the critical path (CN update min-finding) and retry
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- Document achieved frequency in final submission
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### Contest Deliverables
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**Proposal (due Mar 25):**
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- GitHub repo (`chip_ignite`) with README describing the project
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- Project description: LDPC decoder for photon-starved optical comm
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- Architecture overview, target specs, verification plan
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**Final Submission (due Apr 30):**
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| Deliverable | Source |
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| GDSII | OpenLane output from `cf harden` |
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| RTL + testbenches | `chip_ignite/verilog/rtl/` and `verilog/dv/cocotb/` |
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| Gate-level sim passing | `cf verify --all --sim gl` |
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| Precheck passing | `cf precheck` |
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| Firmware source | `chip_ignite/firmware/ldpc_demo/` |
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| PCBA design (KiCad) | `chip_ignite/pcba/` |
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| Mechanical (OpenSCAD) | `chip_ignite/mechanical/` |
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| 3-min demo video | Screen recording of UART decode output + GDS viewer walkthrough |
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| Screenshots (how-to) | Step-by-step: build firmware, program, run demo |
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| Apache 2.0 LICENSE | Repo root |
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| AI disclosure | `docs/ai-disclosure.md` — Claude session logs and prompts |
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### Timeline
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**Week 1 (Feb 25 – Mar 3): Integration & Verification Foundation**
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- Integrate RTL into chip_ignite template (wire into `user_project_wrapper.v`)
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- Generate test vectors from Python model
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- Write cocotb testbenches (all 6 functional tests)
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- Verify RTL simulation passes via `cf verify`
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**Week 2 (Mar 3 – Mar 10): OpenLane Hardening**
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- Create OpenLane config for `ldpc_decoder_top`
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- First synthesis + P&R run at 50 MHz
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- Debug DRC/LVS issues
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- Run STA, document WNS/TNS
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**Week 3 (Mar 10 – Mar 17): Gate-Level Sim & Timing Push**
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- Gate-level simulation of all cocotb tests
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- If timing margin exists, push toward 75 MHz
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- Pipeline critical paths if needed
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- Pass `cf precheck`
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**Week 4 (Mar 17 – Mar 25): PROPOSAL DEADLINE**
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- Polish README with architecture, specs, verification status
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- Submit proposal (repo URL via contest form)
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- Start firmware development in parallel
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**Week 5 (Mar 25 – Apr 7): Firmware & PCBA**
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- Write PicoRV32 firmware (LLR load, decode, UART output)
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- Design PCBA schematic in KiCad (breakout + optical frontend reference)
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- Start PCB layout
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**Week 6 (Apr 7 – Apr 14): PCBA & Mechanical**
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- Complete PCB layout, generate Gerbers
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- Design 3D-printed enclosure in OpenSCAD
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- BOM with Digi-Key part numbers and costs
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**Week 7 (Apr 14 – Apr 21): Documentation & Demo**
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- AI disclosure document
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- Verification report
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- Record 3-min demo video (cocotb sim + GDS walkthrough)
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- How-to screenshots
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**Week 8 (Apr 21 – Apr 30): FINAL SUBMISSION**
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- Final `cf precheck` pass
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- Polish all docs
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- Submit
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**Buffer:** ~1 week of slack distributed across weeks 5–7. Critical path is weeks 1–3 (RTL integration → hardening → GLS).
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---
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## Approach B: Full Reference Design (ASPIRATIONAL)
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Everything in Approach A, plus:
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- **Populated optical frontend** on PCBA — SiPM stand-in (e.g. ON Semi C-Series MicroFC) + TIA (AD8015) + fast comparator (ADCMP607). Analog section designed for single-photon pulse detection.
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- **External MCU** (RP2040) on PCBA for real-time LLR computation from detector output. Receives photon count data, computes Poisson channel LLRs, feeds to Caravel ASIC over SPI.
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- **Actual free-space optical link demo** — modulated laser diode TX (OOK or PPM), receiver board with populated optical frontend, ~1–5m bench-scale link.
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- **More elaborate enclosure** with lens mount (aspheric collimating lens), detector alignment rail, and laser safety labeling.
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- **Firmware targets:** Both PicoRV32 (ASIC-internal decode control) and RP2040 (external LLR computation + system orchestration).
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**Additional BOM cost:** ~$50–100 per unit (SiPM module, TIA, laser diode, lens, RP2040 board).
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**Additional effort:** ~4–6 weeks beyond Approach A. Requires analog PCB design expertise and optical alignment work.
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---
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## Approach C: Silicon-First, Board-Later (ASPIRATIONAL)
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Chip is identical to Approach A (fully hardened, precheck-clean). Difference is in the board and demo:
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- **PCBA:** Full schematic and layout complete in KiCad (includes optical frontend from Approach B), but untested — silicon doesn't return until Oct/Nov 2026.
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- **Firmware:** Compiles and links against Caravel BSP, but validated only in simulation (cocotb + Verilator), not on hardware.
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- **Demo video:** cocotb simulation showing full decode pipeline + OpenLane GDS walkthrough + KiCad 3D board render. No hardware demo.
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- **Mechanical:** Full enclosure design with detector mount, but 3D-printed prototype deferred until silicon arrives.
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**Rationale:** Acknowledges that no contestant can demo on real silicon by April 30 — the shuttle doesn't return until Oct/Nov. Puts all effort into a clean tape-out and thorough documentation, with the physical build planned for silicon return.
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---
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## Long-Term Vision
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After silicon returns (Oct/Nov 2026):
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1. Build and populate full Approach B board
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2. Demonstrate free-space optical link with BAE GMAPD detector
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3. Characterize decoder BER performance on real silicon vs. simulation
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4. Publish results as open-source reference design for photon-starved optical comm
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5. Target applications: CubeSat optical downlinks, underwater optical modems, quantum key distribution post-processing
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