110 lines
3.8 KiB
Systemverilog
110 lines
3.8 KiB
Systemverilog
// LDPC Decoder Top - QC-LDPC Rate 1/8 for Photon-Starved Optical Communication
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// Target: Efabless chipIgnite (SkyWater 130nm, Caravel harness)
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//
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// Code parameters:
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// Rate 1/8, n=256 coded bits, k=32 info bits
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// QC-LDPC with 7x8 base matrix, lifting factor Z=32
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// Offset min-sum decoding, layered scheduling
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//
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// Input: 6-bit signed LLRs (log-likelihood ratios from photon detector)
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// Output: 32 decoded information bits + convergence status
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module ldpc_decoder_top #(
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parameter N_BASE = 8, // base matrix columns
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parameter M_BASE = 7, // base matrix rows
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parameter Z = 32, // lifting factor
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parameter N = N_BASE * Z, // codeword length = 256
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parameter K = Z, // info bits = 32 (rate 1/8)
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parameter Q = 6, // LLR quantization bits (signed)
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parameter MAX_ITER = 30, // maximum decoding iterations
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parameter DC = 8, // check node degree (= N_BASE for regular)
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parameter DV_MAX = 7 // max variable node degree (= M_BASE for regular)
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)(
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input logic clk,
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input logic rst_n,
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// Wishbone B4 pipelined slave interface
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input logic wb_cyc_i,
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input logic wb_stb_i,
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input logic wb_we_i,
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input logic [7:0] wb_adr_i, // byte address (256 bytes address space)
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input logic [31:0] wb_dat_i,
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output logic [31:0] wb_dat_o,
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output logic wb_ack_o,
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// Interrupt (active high, directly to Caravel IRQ)
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output logic irq_o
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);
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// =========================================================================
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// Wishbone register interface
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// =========================================================================
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// Control/status registers
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logic ctrl_start; // pulse: begin decoding
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logic ctrl_early_term; // enable early termination
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logic [4:0] ctrl_max_iter; // max iterations (0 = use MAX_ITER)
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logic stat_busy;
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logic stat_converged;
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logic [4:0] stat_iter_used;
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// LLR input buffer (packed vector for Yosys compatibility)
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logic [N*Q-1:0] llr_input_flat;
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// Decoded output
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logic [K-1:0] decoded_bits;
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logic [7:0] syndrome_weight;
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wishbone_interface #(
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.N(N), .K(K), .Q(Q)
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) u_wb (
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.clk (clk),
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.rst_n (rst_n),
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.wb_cyc_i (wb_cyc_i),
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.wb_stb_i (wb_stb_i),
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.wb_we_i (wb_we_i),
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.wb_adr_i (wb_adr_i),
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.wb_dat_i (wb_dat_i),
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.wb_dat_o (wb_dat_o),
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.wb_ack_o (wb_ack_o),
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.ctrl_start (ctrl_start),
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.ctrl_early_term(ctrl_early_term),
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.ctrl_max_iter (ctrl_max_iter),
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.stat_busy (stat_busy),
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.stat_converged (stat_converged),
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.stat_iter_used (stat_iter_used),
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.llr_input (llr_input_flat),
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.decoded_bits (decoded_bits),
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.syndrome_weight(syndrome_weight),
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.irq_o (irq_o)
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);
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// =========================================================================
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// Decoder core
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// =========================================================================
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ldpc_decoder_core #(
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.N_BASE (N_BASE),
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.M_BASE (M_BASE),
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.Z (Z),
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.Q (Q),
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.MAX_ITER (MAX_ITER),
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.DC (DC),
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.DV_MAX (DV_MAX)
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) u_core (
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.clk (clk),
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.rst_n (rst_n),
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.start (ctrl_start),
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.early_term_en (ctrl_early_term),
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.max_iter (ctrl_max_iter),
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.llr_in (llr_input_flat),
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.busy (stat_busy),
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.converged (stat_converged),
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.iter_used (stat_iter_used),
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.decoded_bits (decoded_bits),
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.syndrome_weight(syndrome_weight)
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);
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endmodule
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