140 lines
4.9 KiB
Systemverilog
140 lines
4.9 KiB
Systemverilog
// Wishbone B4 slave interface for LDPC decoder
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// Compatible with Caravel SoC Wishbone interconnect
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//
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// Register map (byte-addressed):
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// 0x00 CTRL R/W [0]=start (auto-clear), [1]=early_term_en, [12:8]=max_iter
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// 0x04 STATUS R [0]=busy, [1]=converged, [12:8]=iterations_used, [23:16]=syndrome_wt
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// 0x10-0x4F LLR W Channel LLRs packed 5x6-bit per 32-bit word (52 words for 256 LLRs)
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// 0x50 DECODED R 32 decoded info bits
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// 0x54 VERSION R Version/ID register
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module wishbone_interface #(
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parameter N = 256,
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parameter K = 32,
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parameter Q = 6
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)(
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input logic clk,
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input logic rst_n,
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// Wishbone slave
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input logic wb_cyc_i,
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input logic wb_stb_i,
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input logic wb_we_i,
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input logic [7:0] wb_adr_i,
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input logic [31:0] wb_dat_i,
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output logic [31:0] wb_dat_o,
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output logic wb_ack_o,
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// To/from decoder core
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output logic ctrl_start,
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output logic ctrl_early_term,
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output logic [4:0] ctrl_max_iter,
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input logic stat_busy,
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input logic stat_converged,
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input logic [4:0] stat_iter_used,
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output logic [N*Q-1:0] llr_input, // packed LLR vector
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input logic [K-1:0] decoded_bits,
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input logic [7:0] syndrome_weight,
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// Interrupt
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output logic irq_o
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);
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localparam VERSION_ID = 32'h1D01_0001; // LDPC v0.1 build 1
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// Wishbone handshake: ack on valid cycle
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logic wb_valid;
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assign wb_valid = wb_cyc_i && wb_stb_i;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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wb_ack_o <= 1'b0;
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else
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wb_ack_o <= wb_valid && !wb_ack_o; // single-cycle ack
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end
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// =========================================================================
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// Control register
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// =========================================================================
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logic start_pending;
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logic early_term_reg;
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logic [4:0] max_iter_reg;
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// Start is a pulse: set on write, cleared after one cycle
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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start_pending <= 1'b0;
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early_term_reg <= 1'b1; // early termination on by default
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max_iter_reg <= 5'd0; // 0 = use MAX_ITER default
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end else begin
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if (ctrl_start)
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start_pending <= 1'b0;
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if (wb_valid && wb_we_i && !wb_ack_o && wb_adr_i == 8'h00) begin
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start_pending <= wb_dat_i[0];
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early_term_reg <= wb_dat_i[1];
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max_iter_reg <= wb_dat_i[12:8];
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end
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end
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end
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assign ctrl_start = start_pending && !stat_busy;
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assign ctrl_early_term = early_term_reg;
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assign ctrl_max_iter = max_iter_reg;
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// =========================================================================
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// LLR input: pack 5 LLRs per 32-bit word
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// Word at offset 0x10 + 4*i contains LLRs [5*i] through [5*i+4]
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// Bits [5:0] = LLR[5*i], [11:6] = LLR[5*i+1], ... [29:24] = LLR[5*i+4]
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// 52 words cover 260 LLRs (256 used, 4 padding)
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// =========================================================================
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always_ff @(posedge clk) begin
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if (wb_valid && wb_we_i && !wb_ack_o) begin
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if (wb_adr_i >= 8'h10 && wb_adr_i < 8'hE0) begin
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int word_idx;
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word_idx = (wb_adr_i - 8'h10) >> 2;
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for (int p = 0; p < 5; p++) begin
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int llr_idx;
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llr_idx = word_idx * 5 + p;
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if (llr_idx < N)
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llr_input[llr_idx*Q +: Q] <= wb_dat_i[p*Q +: Q];
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end
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end
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end
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end
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// =========================================================================
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// Read mux
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// =========================================================================
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always_comb begin
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wb_dat_o = 32'h0;
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case (wb_adr_i)
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8'h00: wb_dat_o = {19'b0, max_iter_reg, 6'b0, early_term_reg, start_pending};
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8'h04: wb_dat_o = {8'b0, syndrome_weight, 3'b0, stat_iter_used, 6'b0, stat_converged, stat_busy};
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8'h50: wb_dat_o = decoded_bits;
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8'h54: wb_dat_o = VERSION_ID;
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default: wb_dat_o = 32'h0;
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endcase
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end
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// =========================================================================
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// Interrupt: assert when decode completes (busy falls)
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// =========================================================================
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logic busy_d1;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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busy_d1 <= 1'b0;
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irq_o <= 1'b0;
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end else begin
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busy_d1 <= stat_busy;
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// Pulse IRQ on falling edge of busy
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irq_o <= busy_d1 && !stat_busy;
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end
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end
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endmodule
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