Document the full wrapper hardening trail:
- Mar 12-13 wrapper_v2/v3/v4 results, mpw_precheck 17/19, and 5/5 GLS pass
- May 7-11 v6-v11 LVS-cosmetic-fix attempts (all seven failed)
The v6-v11 series tried to eliminate the 208 cosmetic LVS pin-match
errors via per-pin conb_1 tieoffs and placement tweaks. All failed
because the errors are a Magic SPICE-extraction limitation (constant-
tied output nets collapse into shared power/ground at extract time),
not a hardening defect. Documented so future sessions don't re-explore
this dead end.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
- Run 5: syndrome pipeline with serial popcount (no improvement)
- Run 6: balanced popcount adder tree — TT timing MET at 50 MHz
- Run 7 series (8 attempts): LAYER_WRITE pipeline exploration
- LAYER_WRITE split not viable (cell explosion / PnR divergence)
- Yosys synthesis non-determinism documented
- Hold margin sensitivity (0.4/0.2 vs 0.5/0.3) identified
- Run 7h reproduces Run 6 by reusing golden synthesis netlist
Key finding: balanced_popcount synthesis netlist is the golden reference
for all future PnR iterations.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Documents 4 hardening runs with timing/area/DRC results. Identifies
SYNDROME state as critical path bottleneck (222 logic levels, 49 ns)
and proposes 2-stage pipeline fix to meet 50 MHz target.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
20 tasks across 8 weeks covering RTL integration, verification,
OpenLane hardening, firmware, PCBA, and final submission.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Approach A (minimal viable submission) as execution plan,
Approaches B and C documented as aspirational roadmap.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Reuses existing syndrome_wt register and converged flag.
No additional hardware needed on the ASIC.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Adds section 7 covering preamble-less frame sync using syndrome
screening, which was missing from the original report.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Comprehensive report for FPGA partner covering:
- System architecture and channel model
- LDPC decoder hardware blocks
- Code optimization journey (5.23 -> 1.03 photons/slot)
- SC-LDPC threshold saturation results
- RTL implementation plan and area estimates
Includes 10 figures: system architecture, channel model,
degree distributions, FER curves, threshold progressions.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Covers all five studies: rate comparison, base matrix quality,
quantization sweep, Shannon gap, and frame synchronization.
Includes interpretation, recommendations, and reproduction steps.
Key findings: 9 dB gap to Shannon, matrix degree distribution is
the primary bottleneck, 6-bit quantization validated, frame sync
tractable at ~30 us acquisition cost.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Covers frame synchronization prototype (acquisition + re-sync)
and four code analysis studies: rate comparison, base matrix
quality, quantization sweep, and Shannon gap computation.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
